NXP Semiconductors QorIQ LS1043ARDB - TDM Clock or SDHC;USB Selection Register

CPLD_SD1REFCLK_SEL field descriptions
Field Description
0
SD1REFCLK_
SEL
SerDes PLL1 reference clock input selection
0 100 MHz
1 156.25 MHz (default value)
1–7
-
This field is reserved.
6.1.12 TDM clock or SDHC/USB selection register
(CPLD_TDMCLK_MUX_SEL)
Use this register to select TDM clock or SDHC/USB.
Address:
0h base + Bh offset = Bh
Bit 0 1 2 3 4 5 6 7
Read
TDMCLK_
SDHC_
USB_SEL
Reserved
Write
Reset
0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
The register reset value is controlled by SW3[7].•
CPLD_TDMCLK_MUX_SEL field descriptions
Field Description
0
TDMCLK_
SDHC_USB_SEL
TDM clock or SDHC/USB selection
0 TDM_CLK
1 SDHC/USB (default value)
1–7
-
This field is reserved.
Chapter 6 CPLD Programming
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 59