Chapter 6
CPLD Programming
This chapter describes the CPLD register user interface in the LS1043ARDB.
6.1 CPLD memory map / register definitions
The table below shows the memory map for the CPLD registers.
CPLD memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
0 CPLD major version register (CPLD_VER) 8 R 02h 6.1.1/52
1 CPLD minor version register (CPLD_VER_SUB) 8 R 00h 6.1.2/52
2 PCBA version register (CPLD_PCBA_VER) 8 R 05h 6.1.3/53
3 System reset register (CPLD_SYSTEM_RST) 8 R/W 00h 6.1.4/53
4
CPLD override physical switches enable register
(CPLD_SOFT_MUX_ON)
8 R/W 00h 6.1.5/54
5
POR RCW source location register 1
(CPLD_REG_RCW_SRC1)
8 R/W See section 6.1.6/55
6
POR RCW source location register 2
(CPLD_REG_RCW_SRC2)
8 R/W See section 6.1.7/56
7 Flash bank selection register (CPLD_REG_BANK) 8 R/W See section 6.1.8/56
8
System clock single-ended or differential input selection
register (CPLD_SYSCLK_SEL)
8 R/W See section 6.1.9/57
9 UART1 output selection register (CPLD_UART_SEL) 8 R/W See section 6.1.10/58
A
SerDes PLL1 reference clock input selection register
(CPLD_SD1REFCLK_SEL)
8 R/W See section 6.1.11/58
B
TDM clock or SDHC/USB selection register
(CPLD_TDMCLK_MUX_SEL)
8 R/W See section 6.1.12/59
D Status LED control register (CPLD_STATUS_LED) 8 R/W 00h 6.1.13/60
E Global reset register (CPLD_GLOBAL_RST) 8 R/W 00h 6.1.14/60
Table continues on the next page...
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 51
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