NXP Semiconductors QorIQ LX2160A User Manual

QorIQ LX2160A Reference Design
Board Reference Manual
Supports LX2160ARDB Revision B
Document Number: LX2160ARDBRM
Rev. 0, 09/2018

NXP Semiconductors QorIQ LX2160A Specifications

General

Brand	NXP Semiconductors
Model	QorIQ LX2160A
Category	Motherboard
Language	English

Summary

Chapter 1 LX2160ARDB Overview

1.1 Acronyms and abbreviations

Lists and explains acronyms and abbreviations used in the document.

1.2 Related documentation

Lists and explains additional documents and resources for further information.

1.3 Block diagrams

Provides block diagrams showing major functional units of the LX2160A processor and LX2160ARDB.

1.4 Board features

Lists the features of the LX2160ARDB.

1.5 Board top view

Shows the top-side view of the LX2160ARDB.

Chapter 2 LX2160ARDB Functional Description

Power supplies

Discusses the power supplies for the LX2160A processor, DDR4 UDIMM, PHYs, and peripherals.

Clocks

Explains the clock architecture and sources.

DDR interface

Discusses the two high-speed DDR4 memory ports.

SerDes interface

Discusses the SerDes modules and lanes.

Ethernet controller interface

Explains the Ethernet controllers EC1 and EC2.

Ethernet management interface

Discusses EMI1 and EMI2 for controlling PHY transceivers.

eSDHC interface

Discusses the two eSDHC controllers for SD and eMMC.

XSPI interface

Discusses the XSPI interface for flash memories and emulator.

USB interface

Discusses the two USB 3.0 controllers and connectors.

I2C interface

Discusses the I2C buses and multiplexer.

UART interface

Discusses the UART blocks and connectors.

CAN interface

Discusses the CAN modules and transceivers.

JTAG port

Discusses the JTAG connector for debugging.

Interrupt controller

Discusses the generic interrupt controller.

GPIO access

Discusses GPIO access via IRQ and EVT pins.

Temperature measurement

Discusses thermal monitoring diodes and devices.

LEDs

Discusses the onboard LEDs for monitoring system functions.

DIP switches

Explains the DIP switches available on the LX2160ARDB.

System controller

Discusses the CPLD that controls system operation.

2.1 Power supplies

Details the necessary voltages for operation and their derivation.

2.1.1 Primary power supply

Details the external ATX 12V/EPS12V power supply specifications.

2.1.2 Secondary power supplies

Lists secondary power supplies derived from the ATX unit.

2.1.3 Power supply sequence

Details the orderly power-up sequence managed by the CPLD.

2.1.4 Current and power measurement

Describes onboard current and power measurement capabilities.

2.2 Clocks

Explains the clock architecture and sources.

2.3 DDR interface

Discusses the two high-speed DDR4 memory ports.

2.3.1 DDR power

Lists the power supplies for the DDR4 subsystem.

2.4 SerDes interface

Discusses the SerDes modules and lanes.

2.5 Ethernet controller interface

Explains the Ethernet controllers EC1 and EC2.

2.5.1 IEEE 1588 interface

Discusses support for IEEE 1588 precision time protocol.

2.6 Ethernet management interface

Discusses EMI1 and EMI2 for controlling PHY transceivers.

2.7 eSDHC interface

Discusses the two eSDHC controllers for SD and eMMC.

2.8 XSPI interface

Discusses the XSPI interface for flash memories and emulator.

2.9 USB interface

Discusses the two USB 3.0 controllers and connectors.

2.10 I2C interface

Discusses the I2C buses and multiplexer.

2.11 UART interface

Discusses the UART blocks and connectors.

2.12 CAN interface

Discusses the CAN modules and transceivers.

2.13 JTAG port

Discusses the JTAG connector for debugging.

2.14 Interrupt controller

Discusses the generic interrupt controller.

2.15 GPIO access

Discusses GPIO access via IRQ and EVT pins.

2.16 Temperature measurement

Discusses thermal monitoring diodes and devices.

2.17 LEDs

Discusses the onboard LEDs for monitoring system functions.

2.17.1 Multi-status LEDs

Describes the functions of the multi-status LED arrays.

2.18 DIP switches

Explains the DIP switches available on the LX2160ARDB.

2.19 System controller

Discusses the CPLD that controls system operation.

2.19 System configuration

Explains how switches configure the system.

2.19.2 System startup

Details the system startup sequence managed by the CPLD.

Chapter 3 Qixis Programming Model

3.1 Register Conventions

Defines conventions for register addresses and reserved bits.

3.2 Resets

Defines reset values for registers and reset actions.

3.3 Identification Registers

Registers that identify the board and its revisions.

3.4 Identification (ID)

The ID register contains a unique classification number for the board.

3.5 Board Version (VER)

Records PCB board and architecture version information.

3.6 Qixis Version (QVER)

Contains the major version information of the Qixis system controller.

3.7 Programming Model (MODEL)

Contains information about the software programming model and BOM.

3.8 Minor Revision (MINOR)

Obtains CPLD build information and minor revision details.

3.9 Control and Status Registers

Registers that control Qixis operations and monitor system status.

3.10 General Control (CTL)

Controls various aspects of the target system and LEDs.

3.11 Auxiliary (AUX)

Register used by software to store information.

3.12 System Status (STAT_SYS)

Reports general system status, including BootBox mode and alarms.

3.13 Alarm (ALARM)

Detects and reports alarms raised in the QIXIS system.

3.14 Presence Detect 1 (STAT_PRES1)

Detects processor presence and type.

3.15 Presence Detect 2 (STAT_PRES2)

Detects installation of cards in PCI Express or SGMII slots.

3.16 LED Control (LED)

Directly controls monitoring LEDs for debugging or status.

3.17 Reconfiguration Registers

Controls the reconfiguration system for board/processor settings.

3.18 Reconfiguration Control (RCFG)

Controls the reconfiguration sequencer.

3.19 SFP CSR 1 (SFP1)

Controls and monitors the zQSFP+ cage used with 40GE PHY.

3.20 SFP CSR 2 (SFP2)

Controls and monitors the SFP+ cage used with 25G PHY #1.

3.21 SFP CSR 3 (SFP3)

Controls and monitors the SFP+ cage used with 25G PHY #2.

3.22 LOS Status (LOS)

Reports LOS or LOL for various interfaces.

3.23 Watchdog (WATCH)

Selects the watchdog timer value for reconfiguration processes.

3.24 Power Control/Status Registers

Monitors general and individual power status.

3.25 Power Control 2 (PWR_CTL2)

Controls system power-on/power-off events.

3.26 Power Event Trace (PWR_EVENT)

Records events that caused power-on or -off.

3.27 Power Status 0 (PWR_MSTAT)

Monitors the overall power status of the board.

3.28 Power Status 1 (PWR_STAT1)

Monitors the status of individual power supplies.

3.29 Power Status 2 (PWR_STAT2)

Monitors various power statuses.

3.30 Clock Control Registers

Control programmable clock synthesizers for clocks.

3.31 Clock Speed 1 (CLK_SPD1)

Reports user-selectable speed settings for SYSCLK and DDRCLK.

3.32 Clock ID/Status (CLK_ID)

Identifies the arrangement of clock control registers.

3.33 Reset Control Registers

Handles reset behavior configuration and monitoring.

3.34 Reset Control (RST_CTL)

Configures or triggers reset actions.

3.35 Reset Status (RST_STAT)

Reports the current status of various reset-related signals.

3.36 Reset Event Trace (RST_REASON)

Reports the cause of the most-recent reset cycle.

3.37 Reset Force 1 (RST_FORCE1)

Forces reset to a particular device.

3.38 Reset Force 2 (RST_FORCE2)

Forces reset to selected devices.

3.39 Reset Force 3 (RST_FORCE3)

Forces reset to selected device interfaces.

3.40 Reset Mask 1 (RST_MASK1)

Blocks reset to a particular device.

3.41 Reset Mask 2 (RST_MASK2)

Masks selected reset sources.

3.42 Reset Mask 2 (RST_MASK3)

Masks selected reset sources.

3.43 Board Configuration Registers

Controls the configuration of the board.

3.44 Board Configuration 0 (BRDCFG0)

Used to select IFC and QSPI boot devices.

3.45 Board Configuration 1 (BRDCFG1)

Shows/controls SYSCLK and DDRCLK speeds.

3.46 Board Configuration 2 (BRDCFG2)

Reports SerDes clock speeds and PCIe clock settings.

3.47 Board Configuration 3 (BRDCFG3)

Reports SerDes clock speeds for block 3.

3.48 Board Configuration 4 (BRDCFG4)

Controls general board configuration.

3.49 DUT Configuration Registers

Registers controlling the configuration of the DUT.

3.50 DUT Configuration 0 (DUTCFG0)

Selects the boot device used upon reset.

3.51 DUT Configuration 1 (DUTCFG1)

Holds LSB of cfg_rcw_src values (ignored for LX2160ARDB).

3.52 DUT Configuration 2 (DUTCFG2)

Manages processor device selection (SVR) and test features.

3.53 DUT Configuration 6 (DUTCFG6)

Samples device-specific test modes.

3.54 DUT Configuration 11 (DUTCFG11)

Controls CFG_ENG_USE signals for clock modes.

3.55 DUT Configuration 12 (DUTCFG12)

Provides general-purpose GPCFG signals.

3.56 IRQ Management Registers

Monitor and control interrupt behavior.

3.56.1 Interrupt Assignments

Lists interrupt assignments and their control status.

3.57 Interrupt Status 0 (IRQSTAT0)

Reports the current level of IRQ0..IRQ7 signals.

3.58 Interrupt Status 1 (IRQSTAT1)

Reports IRQ8..IRQ12 and TA_TMP_DETECT_B status.

3.59 Interrupt Control 0 (IRQCTL0)

Defines interrupt output modes for IRQ[0:3].

3.60 Interrupt Control 2 (IRQCTL2)

Defines interrupt output modes for IRQ[8:11].

3.61 Interrupt Drive 0 (IRQDRV0)

Allows control of selected interrupt pins.

3.62 Interrupt Drive 1 (IRQDRV1)

Allows control of selected interrupt pins.

3.63 Interrupt Drive 2 (IRQDRV2)

Allows control of selected interrupt pins.

3.64 Interrupt Drive 5 (IRQDRV5)

Allows control of selected interrupt pins.

3.65 Core Management Space Registers

Registers for accessing internal Qixis control registers.

3.65.1 CMS Registers

Defines registers for Core Management Space.

3.66 Core Management Address (CMSA)

Selects internal core management registers for access.

3.67 Core Management Data (CMSD)

Contains the value of a CMS register selected by CMSA.

3.68 Switch Manager Registers

Registers to control/monitor switch sampling.

3.69 Switch Control (SWS_CTL)

Manages the switch sampler.

3.70 Switch Sample Status (SWS_STAT)

Reports update activity from the serial switch sampler.