NXP Semiconductors QorIQ LX2160A - 3.31 Clock Speed 1 (CLK_SPD1)

3.31.1 Address
Register Offset
CLK_SPD1 030h
3.31.2 Function
The CLK_SPD1 register is used to report the user-selectable speed settings (typically
from switches) for the SYSCLK and DDRCLK clocks.
Values in the CLK_SPD1 register are used by boot software accurately initialize timing-
dependent parameters, such as for UART baud rates, I2C clock rates, and DDR memory
timing.
3.31.3 Diagram
Bits
7 6 5 4 3 2 1 0
R DDRCLK SYSCLK
W
NONE 0000 0000
3.31.4 Fields
Field Function
7-4
DDRCLK
DDRCLK Rate Selection:
0000= 100.00 MHz (fixed)
Other values are Reserved.
3-0
SYSCLK
SYSCLK Rate Selection:
0000= 100.00 MHz (fixed)
Other values are Reserved.
Clock ID/Status (CLK_ID)
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
96 NXP Semiconductors