NXP Semiconductors QorIQ LX2160A - 3.55 DUT Configuration 12 (DUTCFG12)

Field Function
1= Processor uses single-ended SYSCLK input.
6
ENGUSE1
ENG_USE1: Reserved (cfg_enguse1):
1= Default value for reserved pins.
5
ENGUSE2
ENG_USE2: DDR Clock Source Select (cfg_enguse2):
0= DDR clocked from DDRCLK pin (default).
1= DDR clocked from differential SYSCLK.
4-0
-
Reserved.
3.55 DUT Configuration 12 (DUTCFG12)
3.55.1 Address
Register Offset
DUTCFG12 06Ch
3.55.2 Function
The DUTCFG12 register is used to provide the general-purpose GPCFG signals.
These settings are sampled by the processor for customers to use as desired, but have no
hardware effects.
3.55.3 Diagram
Bits
7 6 5 4 3 2 1 0
R
GCA
W
RRST
SW_GPIN 111111
Chapter 3 Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 119