2.5.1 IEEE 1588 interface
The LX2160A processor provides support for the IEEE 1588
™
precision time protocol
(PTP), which works in tandem with the Ethernet controllers to time-stamp the incoming
packets. A 12-pin header is provided on the board to allow access to the IEEE 1588
system (see figure below).
LX2160A
I1588_PULSE_OUT[2:1]
I1588_ALARM_OUT[1:2]
I1588_TRIG_IN[1:2]
TSM-106-01-S-DV-A-P
TSEC_1588_ALARM_OUT[1:2]
TSEC_1588_TRIG_IN[1:2]
TSEC_1588_CLK_OUT
TSEC_1588_CLK_IN
TSEC_1588_PULSE_OUT[1:2]
Clock mux
CPLD
I1588_CLK_OUT
1588 access header
I1588_CLK_IN
RST_IEEESLT_B
1
2
3
4
5
6
7
8
9
10
11
12
OVDD (1.8 V)
(1,3)
(2,4)
(5,7)
(8)
(6)
RCLK0
IEEE_RCLK0
(9)
(10)
IEEETEST_CLKIN
3V3
CFG_IEEE_SRC
Si5341B
CLK_1588_CGEN
Figure 2-12. IEEE 1588 architecture
The table below lists the testing options provided by the IEEE 1588 test header.
Table 2-8. IEEE 1588 port
IEEE 1588 feature Specifications Description
Clocks Input clock Ethernet reference clock (to processor) is driven from an onboard 125
MHz oscillator source. Under software configuration, it may be clocked
from the IEEE 1588 header instead.
Output clock Ethernet output clock is driven to the IEEE 1588 header
Signals Other related signals All remaining IEEE 1588 signals are connected to the dedicated header
pins
2.6 Ethernet management interface
The LX2160ARDB has two Ethernet management interfaces, EMI1 and EMI2, for
controlling PHY transceivers. The figure below shows the PHY device connections.
Chapter 2 LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 35
To Next Page
Loading...
