NXP Semiconductors QorIQ LX2160A - 3.47 Board Configuration 3 (BRDCFG3)

3.46.2 Function
The BRDCFG2 register reporst SerDes clock speeds for SerDes blocks 1 and 2. PCIe
clocks may be fixed or spread-spectrum enabled, as selected by BRDCFG4.SPREAD.
3.46.3 Diagram
Bits
7 6 5 4 3 2 1 0
R SD1CK1 SD1CK2 SD2CK1 SD2CK2
W
RRST
CPU_ID 11 00 00
3.46.4 Fields
Field Function
7-6
SD1CK1
SerDes1 Clock #1 (F) Rate:
11= 161.1328125 MHz (fixed)
5-4
SD1CK2
SerDes1 Clock #2 (S) Rate:
11= 161.1328125 MHz (fixed)
3-2
SD2CK1
SerDes2 Clock #1 (F) Rate:
00= 100.0000000 MHz (fixed)
1-0
SD2CK2
SerDes2 Clock #2 (S) Rate:
00= 100.0000000 MHz (fixed)
3.47 Board Configuration 3 (BRDCFG3)
3.47.1 Address
Register Offset
BRDCFG3 053h
Chapter 3 Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 111