Table 1-3. LX2160ARDB features (continued)
LX2160ARDB feature Specification Description
Ethernet Two tri-speed RGMII
interfaces
• 10 Mb / 100 Mb / 1 Gb Ethernet is supported
• An RJ45 connector with link and activity status is used with each
RGMII interface
• IEEE 1588
™
precision time protocol (PTP) is supported through an
onboard header (J29)
Clocks System clock
(SYSCLK) and DDR
clock (DDRCLK)
• 100 MHz differential clock to DIFF_SYSCLK
• 100 MHz single-ended clock to DDRCLK
SerDes clocks • 161.1328125 MHz clock to SerDes1 PLL 1 and PLL 2
• 100 MHz clock to SerDes2 PLL 1 and PLL 2
• 100 MHz clock to SerDes3 PLL 1 and PLL 2
• 100 MHz clock to AQR107 10 GbE PHY 1 and 2
• 25 MHz clock to IN112525 25 GbE PHY
• 156.25 MHz clock to CS4223 40 GbE PHY
• 100 MHz clock to x4 and x8 PCIe slots
Ethernet clocks 125 MHz clocks to Ethernet controllers and IEEE 1588 port
Power supplies • 12 V, 5 V, 3.3 V, and 5 V (standby) ATX power supplies
• 0.8 V (VDD) for the LX2160A core
• 1.2 V (G1VDD and G2VDD) for DDR4
• 0.92 V (SD_SVDD) for SerDes cores
• 1.8 V (SD_OVDD) for SerDes I/O drivers
• 0.9 V (SD_AVDD) for SerDes PLLs
• 1.8 V (OVDD) for general I/O
• 1.8 V (standby) and 3.3 V (standby) for CPLD core and I/O
• 0.8 V for USB_SVDD and USB_SDVDD
• 3.3 V for USB_HVDD
• 0.8 V (TA_BB_VDD) for the LX2160A secure monitor
• 1.8 V for TA_PROG_SFP and PROG_MTR
Debug features Arm Cortex 10-pin JTAG connector
Package • Package type is 40 mm x 40 mm, 1517 Flip Chip, Plastic-ball, Grid
Array (FC-PBGA)
• Socket and heat sink are included
System logic CPLD • Manages the following:
• System power sequencing
• System reset sequencing
• System and SerDes clock speed selections
• SoC POR configuration at reset
• Implements registers for system control and monitoring
• General fault monitoring and logging
1.5 Board top view
The figure below shows the top-side view of the LX2160ARDB.
Board top view
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
14 NXP Semiconductors
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