NXP Semiconductors QorIQ LX2160A - 3.49 DUT Configuration Registers; 3.50 DUT Configuration 0 (DUTCFG0)

Field Function
SPREAD 0= Disabled: PCI-Express 100 MHz clocks (all) are locked.
1= Enabled: PCI-Express 100 MHz clocks (all) are spread-spectrum modulated.
3.49 DUT Configuration Registers
This block of registers control the configuration of the DUT (Device Under Test).
DUTCFG registers, unlike BRDCFG registers, are not always driven - they are driven
only during the reset configuration sampling interval (PORESET_B assertion), and
remain tri-stated thereafter. Refer to the device hardware specification for hardware pin-
sampled timing parameters.
3.50 DUT Configuration 0 (DUTCFG0)
3.50.1 Address
Register Offset
DUTCFG0 060h
3.50.2 Function
The DUTCFG0 register is used to select the boot device used upon reset (cfg_rcw_src).
3.50.3 Diagram
Bits
7 6 5 4 3 2 1 0
R
RCWSRC
W
RRST
0000 SW_RCW_SRC
DUT Configuration Registers
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
114 NXP Semiconductors