2.15 GPIO access
The LX2160A processor has no dedicated general-purpose input/output (GPIO) pins.
Instead, GPIO functions are multiplexed internally onto other signals, which must be
disabled before using the GPIO functions. For the LX2160ARDB, GPIO access is
provided through the IRQ pins IRQ[0:11] and EVT pins EVT[0:4] but only when those
pins are not used for IRQ or other purposes. The following figure shows the GPIO access
header.
LX2160A
GPIO
event
header
90120-0125
4.7 K (weak)
(17 places)
OVDD
4
3
2
1
5
OVDD (1.8 V)
PHY_25G_LOL/IRQ1
IRQ6
IRQ_FAN_B/IRQ7
PHY_25G_LOL/IRQ9
PHY_25G_LOL/IRQ10
IRQ_QSFP_B/IRQ11
IRQ_40GE_B/IRQ0
IRQ_10G_PHY1_B/IRQ2
IRQ_10G_PHY2_B/IRQ3
IRQ_EPHY1_B/IRQ4
IRQ_EPHY2_B/IRQ5
IRQ_RTC_B/IRQ8
EVT0
EVT1
EVT2
EVT3
EVT4
CS4223 40 GbE PHY
AQR107 10 GbE PHY #1
AQR107 10 GbE PHY #2
AR8035 1 GbE PHY #1
AR8035 1 GbE PHY #2
RTC
IN112525 25 GbE PHY
IN112525 25 GbE PHY
IN112525 25 GbE PHY
zQSFP+ 40 GbE module
EMC2305 fan controller
Figure 2-25. GPIO interface
By programming the RCW “IRQ_EXT” field properly, an unused IRQ pin can be
reassigned to GPIO purposes. Event signals from EVT pins EVT[0:4] flow through a 5-
pin GPIO header.
The table below shows the GPIO mapping in the LX2160ARDB.
GPIO access
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
50 NXP Semiconductors
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