Chapter 3
Qixis Programming Model
The system controller CPLD contains many registers which may be used to monitor and
control both the processor and hardware on the RDB. A 3-pin header on the system
allows remote monitoring/control of the system, or the processor can access these
registers itself using I2C port 1, using the standard address of 0x66. This address and the
register layout adheres to the QixMin (minimal Qixis) standards, allowing easier code
reuse across platforms. This chapter explains each of the registers in the register block.
This table shows the register memory map for Qixis.
Table 3-1. Qixis Register Memory Map
Offset Register Width
(In bits)
Access Reset value
000h Identification (ID) 8 RO 01000010b
001h Board Version (VER) 8 RO 11b
002h Qixis Version (QVER) 8 RO 00000001b
003h Programming Model (MODEL) 8 RO 01000000b
004h Minor Revision (MINOR) 8 RW 00000101b
005h General Control (CTL) 8 RW 00000x00b
006h Auxiliary (AUX) 8 RW 00000000b
009h System Status (STAT_SYS) 8 RO 000x0000b
00Ah Alarm (ALARM) 8 RO 10000010b
00Bh Presence Detect 1 (STAT_PRES1) 8 RO 0xx0xxxxb
00Ch Presence Detect 2 (STAT_PRES2) 8 RO xxxxxx11b
00Eh LED Control (LED) 8 RW 00000000b
010h Reconfiguration Control (RCFG) 8 RW 0010x00xb
018h SFP CSR 1 (SFP1) 8 RW 10000000b
019h SFP CSR 2 (SFP2) 8 RW 10110000b
01Ah SFP CSR 3 (SFP3) 8 RW 10110000b
01Dh LOS Status (LOS) 8 RO 00000000b
01Fh Watchdog (WATCH) 8 RW xxxxxxxb
021h Power Control 2 (PWR_CTL2) 8 RW 00000000b
022h Power Event Trace (PWR_EVENT) 8 RO 00000000b
Table continues on the next page...
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 65
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