NXP Semiconductors QorIQ LX2160A - Page 66

Table 3-1. Qixis Register Memory Map (continued)
Offset Register Width
(In bits)
Access Reset value
024h Power Status 0 (PWR_MSTAT) 8 RO 110010xxb
025h Power Status 1 (PWR_STAT1) 8 RO 11111111b
026h Power Status 2 (PWR_STAT2) 8 RO 1xx11111b
030h Clock Speed 1 (CLK_SPD1) 8 RO 00000000b
033h Clock ID/Status (CLK_ID) 8 RO 00000000b
040h Reset Control (RST_CTL) 8 RW 00xx0000b
041h Reset Status (RST_STAT) 8 RO 00000000b
042h Reset Event Trace (RST_REASON) 8 RO xxxx0000b
043h Reset Force 1 (RST_FORCE1) 8 RW 00000000b
044h Reset Force 2 (RST_FORCE2) 8 RW 00000000b
045h Reset Force 3 (RST_FORCE3) 8 RW 00000000b
04Bh Reset Mask 1 (RST_MASK1) 8 RW 00000000b
04Ch Reset Mask 2 (RST_MASK2) 8 RW 00000000b
04Dh Reset Mask 2 (RST_MASK3) 8 RW 00000000b
050h Board Configuration 0 (BRDCFG0) 8 RW xxx00000b
051h Board Configuration 1 (BRDCFG1) 8 RO 00000000b
052h Board Configuration 2 (BRDCFG2) 8 RO xxxx0000b
053h Board Configuration 3 (BRDCFG3) 8 RO 00000000b
054h Board Configuration 4 (BRDCFG4) 8 RW 000x0x0xb
060h DUT Configuration 0 (DUTCFG0) 8 RW 0000xxxxb
061h DUT Configuration 1 (DUTCFG1) 8 RW xxxxxxxb
062h DUT Configuration 2 (DUTCFG2) 8 RW xxxxxxx1b
066h DUT Configuration 6 (DUTCFG6) 8 RW 1xxxxxxxb
06Bh DUT Configuration 11 (DUTCFG11) 8 RW xxxxxxxxb
06Ch DUT Configuration 12 (DUTCFG12) 8 RW xxxxxxxxb
090h Interrupt Status 0 (IRQSTAT0) 8 RO 11xxxx11b
091h Interrupt Status 1 (IRQSTAT1) 8 RO 111111xxb
094h Interrupt Control 0 (IRQCTL0) 8 RW 00000000b
096h Interrupt Control 2 (IRQCTL2) 8 RW 00000000b
098h Interrupt Drive 0 (IRQDRV0) 8 RW 00000000b
099h Interrupt Drive 1 (IRQDRV1) 8 RW 00000000b
09Ah Interrupt Drive 2 (IRQDRV2) 8 RW 00000000b
09Dh Interrupt Drive 5 (IRQDRV5) 8 RW 00000000b
0D8h Core Management Address (CMSA) 8 RW 00000000b
0D9h Core Management Data (CMSD) 8 RW 00000000b
0DCh Switch Control (SWS_CTL) 8 RW 00000101b
0DDh Switch Sample Status (SWS_STAT) 8 RO 10000000b
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
66 NXP Semiconductors