Table 2-26. Startup sequence (continued)
Controller Step Action Description
4 Drive configuration values. Reset-sampled configuration signals are driven:
• CFG_RCW_SRC[3:0]
• CFG_SVR[0:1]
• CFG_ENG_USE[0:2]
• CFG_SOC_USE
• CFG_GPIN[7:6]
Static (constant) configuration signals are driven:
• CFG_XSPI_MAP[0:3]
• CFG_MUX_EC2
• CFG_IEEE_SRC
• CFG_CAN_EN_B
• CFG_40GE_ROM
• CFG_SPREAD
• CFG_MEM_WP
• CFG_CLKEN_SLOT[1:2]
The CFG_DRV_B signal is asserted now, to help with
the few configuration signals that cannot be driven by the
CPLD.
5 Release resets. Release all resets shown in reset sequencer step 1.
The processor samples reset pins at this time.
6 Tristate reset-sampled pins. Three SYSCLK periods after step 5:
De-assert CFG_DRV_B.
Tristate configuration signals drive outputs.
This ensures proper configuration hold time.
The CPLD is no longer involved in reset activity.
7 Processor reset. The LX2160A processor begins loading RCW data from
the specified RCW source location.
When RCW loading is complete, the LX2160A processor
de-asserts HRESET_B and ASLEEP.
If RCW data is correct, then the system will start running
the code. If there is an error, then RESET_REQ_B is
asserted and the system halts.
8 Reset sequence complete. The CPLD has finished reset management.
The reset sequencer watches for reset switch events and
will restart at reset sequencer step 1 if any are detected.
System controller
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
64 NXP Semiconductors
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