Table 1-3. LX2160ARDB features
LX2160ARDB feature Specification Description
Processor 16-core processor 16 Arm
®
Cortex
®
-A72 processor cores based on 32-/64-bit Armv8
architecture, supporting speeds of up to 2.2 GHz
NOTE:
For more details on the LX2160A processor, see QorIQ LX2160A
Family Reference Manual.
DDR memory Two 72-bit DDR4
ports (64-bit data, 8-bit
ECC)
Each DDR4 port supports:
• Two 288-pin DIMM connectors
• Four chip selects
• Single-/dual-rank, unbuffered/registered DDR4 memory modules
• 64-bit data bus
• x4, x8, and x16 data width memory
• Data rates of up to 3.2 GigaTransfers/second (GT/s)
• Double-bit error detection and single-bit error correction ECC (8-bit
check word across 64-bit data)
High-speed serial ports
(SerDes)
Three SerDes
controllers (24 lanes)
• SerDes1:
• Lanes 0-1: Supports two 10 GbE RJ45 USXGMII connectors,
each connected through an Aquantia AQR107 PHY
• Lanes 2-3: Supports two 25 GbE SFP+ modules, connected
through an Inphi IN112525 PHY
• Lanes 4-7: Supports one 40 GbE (40G-SR4, 40G-CR4, or
40G-KR4) QSFP+ module, connected through an Inphi
CS4223 PHY
• SerDes2:
• Lanes 0-3: Supports one PCIe x4 (Gen 1/2/3/4) connector
• Lanes 4-7: Supports four SATA 3.0 connectors
• SerDes3:
• Lanes 0-7: Supports one PCIe x8 (Gen 1/2/3/4) connector
• Each SerDes lane supports speeds of up to 25 GHz
eSDHC eSDHC1 Supports a secure digital (SD) connector (J42) for connecting an SD card
eSDHC2 Supports 128 GB Micron MTFC128GAJAECE-IT embedded multimedia
card (eMMC), supporting HS-400 high-speed transfer mode
Octal SPI (XSPI) One XSPI controller
(XSPI_A)
• Supports two 64 MB onboard octal SPI flash memories
• Supports a QSPI emulator for offboard QSPI emulation
I2C Six I2C controllers
(I2C1, I2C2, I2C3,
I2C4, I2C5, and I2C6)
• Most system devices (other than UEFI) are accessed via I2C1,
which is multiplexed to isolate address conflicts and reduce
capacitive load
• I2C1 is translated to 3V3_SB, allowing programming access to
devices, such as power controllers, clocks, and memories, while the
system is off
• I2C2 is only used for SDHC1_CD_B and SDHC1_WP
• I2C3 is only used for CAN1 input/output
• I2C4 is only used for CAN2 input/output
• I2C5 is used for UEFI support (memory and RTC)
• I2C6 is used for optional AQR107 PHY access
Serial ports Two UART ports
(UART1 and UART2)
A dual-stack DB9 male connector providing two UART connectors, each
connected through an RS-232 transceiver
USB 3.0 Two high-speed USB
3.0 ports with
integrated PHYs
• Supports super-speed (5 Gbit/s), high-speed (480 Mbit/s), full-speed
(12 Mbit/s), and low-speed (1.5 Mbit/s) operations
• USB#1 3.0 port is connected to a Type A host connector
• USB#2 3.0 port is configured as On-The-Go (OTG) with a Micro-AB
connector
Table continues on the next page...
Chapter 1 LX2160ARDB Overview
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 13
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