NXP Semiconductors QorIQ LX2160A - 3.40 Reset Mask 1 (RST_MASK1)

3.40.1 Address
Register Offset
RST_MASK1 04Bh
3.40.2 Function
The RST_MASKn registers are used to block reset to a particular device, independent of
the general reset sequencer. As long as a bit is set to 1, the reset signal to that device or
devices will be blocked.
RST_MASKn bits have the same bit definition as their counterparts in RST_FORCEn;
refer to Table 5-53 for details.
Note that RST_MASK bits are cleared on AUX reset, and so are usually only cleared by
software. This is very different from the RST_FORCE registers.
3.40.3 Diagram
Bits
7 6 5 4 3 2 1 0
R
CLK XSPI QSFP I2CMUX EMMC MEM3 MEM2 MEM1
W
ARST 0 0 0 0 0 0 0 0
3.40.4 Fields
Field Function
7
CLK
1= Mask RST_CLKGEN_B.
6
XSPI
1= Mask RST_XSPI_B.
5
QSFP
1= Mask RST_QSFP_B.
4
I2CMUX
1= Mask RST_I2CMUX_B.
3 1= Mask RST_EMMC _B
Table continues on the next page...
Chapter 3 Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 105