Table 2-24. Processor configuration settings (continued)
Configuration signal LX2160A primary
signal
DIP switch CPLD register Description
CFG_ENG_USE1 UART1_RTS_B SW2[7] DUTCFG11[6] Undefined option
CFG_ENG_USE2 UART2_RTS_B SW2[8] DUTCFG11[5] Specifies whether DDRCLK pin or
differential SYSCLK is used to clock
DDR
CFG_SOC_USE USB1_DRVVBUS SW3[4] DUTCFG6[0] Undefined option
CFG_GPIN[7:6] SDHC2_DAT[3:2] SW4[7:8] DUTCFG12[7:6] User defined
TBSCAN_EN_B TBSCAN_EN_B SW4[4] CTL[7] Controls whether the JTAG operates
in Boundary Scan or Debug mode
1. TEST_SEL_B is a static signal (constantly driven), unlike most other processor configuration signals.
All other configuration signals are static and unrelated to the processor. The following
table summarizes these configuration signals.
Table 2-25. Non-processor configuration settings
Configuration signal DIP switch CPLD register Description
CFG_XSPI_MAP[0:3] SW1[6:8] BRDCFG0[7:5] Controls how XSPI_A chip-selects are connected
to devices/peripherals
CFG_MUX_EC2 - BRDCFG4[7] Controls the configuration of Ethernet controller 2
CFG_IEEE_SRC - BRDCFG4[6] Selects the source for IEEE clock
CFG_CAN_EN_B - BRDCFG4[5] Enables/disables CAN transceivers
CFG_40GE_ROM SW2[2] BRDCFG4[4] Controls the configuration of the CS4223 40 GbE
PHY
CFG_SPREAD SW2[1] BRDCFG4[0] Controls whether clocks for PCIe slots are
spread-spectrum modulated or fixed
CFG_MEM_WP SW4[3] CTL[3] Allows/prevents write to SYSID and I2C flash
2.19.2 System startup
The system controller manages the orderly startup of the system by managing power
enables and reset assertion (including device configuration), in the order shown in the
table below.
Table 2-26. Startup sequence
Controller Step Action Description
Power sequencer 1 Wait for power-on event. Triggered by the SW_PWR_B signal, or by setting switch
SW_AUTO_ON=1.
2 Enable ATX power supply. Enable ATX PSU, wait for it to report “power good”.
LX2160A PORESET_B is asserted during power-up.
Table continues on the next page...
System controller
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
62 NXP Semiconductors
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