2.19.1 System configuration
The system controller uses switches to configure the target system into various modes.
Switches are sampled and stored in BRDCFG and DUTCFG registers. BRDCFG
registers are always active, and software may change them to result in immediate changes
to the system configuration. DUTCFG registers are used to control processor
configuration pins that are only sampled during PORESET_B, such as RCW_SRC in
DUTCFG0. Changes to DUTCFG registers only take effect on the next reset or
reconfiguration event. The following figure shows the configuration hardware
arrangement.
Figure 2-29. Configuration sampling
Note that switches cause a short to ground when closed. To make it easier to set and read
switches, values are inverted in the CPLD, so that when a switch is on, the value used is
1.
All switches can be read from software to easily determine the system configuration for
reporting purposes (see the "Core Management Space Registers" section of the "CPLD
Programming Model" chapter).
The table below describes the LX2160A reset configuration signals.
Table 2-24. Processor configuration settings
Configuration signal LX2160A primary
signal
DIP switch CPLD register Description
CFG_RCW_SRC3 CLK_OUT SW1[1:4] DUTCFG0[3:0] Specifies RCW fetch location
CFG_RCW_SRC2 ASLEEP
CFG_RCW_SRC1 UART1_SOUT
CFG_RCW_SRC0 UART2_SOUT
CFG_SVR[0:1] XSPI1_A_CS[0:1]_B SW3[2:3] DUTCFG2[2:1] Silicon variations
TEST_SEL_B
1
TEST_SEL_B SW3[1] DUTCFG2[0] Silicon variations
CFG_ENG_USE0 XSPI1_A_SCK SW2[6] DUTCFG11[7] Specifies whether single ended or
differential clock is used in the SoC
Table continues on the next page...
Chapter 2 LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 61
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