NXP Semiconductors QorIQ LX2160A - 2.5 Ethernet controller interface

LX2160A
Lanes 0/H 1/G 2/G 3/E 4/D 5/C 6/B 7/A
Protocol
19
XFI.3 XFI.4 25GE.5 25GE.6
Clocks
LX2160A
Lanes 0/A 1/B 2/C 3/D 4/E 5/F 6/G 7/H
Protocol
5
SATA.3 SATA.4 SATA.1 SATA.2
Clocks
LX2160A
Lanes 0/A 1/B 2/C 3/D 4/E 5/F 6/G 7/H
Protocol
2
Clocks
SerDes 3 : x8 : BackSide
PCIe.5 x8
100.00 MHz
SerDes 2 : x8 : FrontSide
PCIe.3 x4
100.00 MHz
100.00 MHz
SerDes 1 : x8 : FrontSide
40GE.2
161.1328125 MHz
161.1328125 MHz
161.1328125 MHz
Figure 2-10. SerDes protocol combinations
The table below shows the LX2160ARDB SerDes assignments when the LX2160A
processor is used.
Table 2-7. SerDes assignments for LX2160A processor
SerDes
module
Lane Connectivity Port
1 H / 0 Aquantia AQR107 10 GbE PHY #1 2x 10 GbE RJ45 USXGMII magnetic jacks (10G
MAC3/4)
G / 1 Aquantia AQR107 10 GbE PHY #2
F-E / 2-3 Inphi IN112525 25 GbE PHY 2x 25 GbE SFP+ fiber transceiver cages (25G
MAC5/6)
D-A / 4-7 Inphi CS4223 40 GbE PHY 40 GbE QSFP+ fiber transceiver cage (40G
MAC2)
2 A-D / 0-3 PCI Express (Gen 1/2/3/4) PCI Express x4 connector (slot 1)
1
E / 4 SATA SATA header 1
F / 5 SATA SATA header 2
G / 6 SATA SATA header 3
H / 7 SATA SATA header 4
3 A-H / 0-7 PCI Express (Gen 1/2/3/4) PCI Express x8 connector (slot 2)
1. A right-angle adapter is required to connect a PCIe Gen 1/2/3 connector. No adapter is required when using a PCIe Gen 4
connector.
NOTE
No muxes or other configuration is required for SerDes
operation.
Chapter 2 LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 33