NXP Semiconductors QorIQ LS1043ARDB - System Clock Input Selection Register

CPLD_REG_BANK field descriptions (continued)
Field Description
3–7
-
This field is reserved.
6.1.9 System clock single-ended or differential input selection
register (CPLD_SYSCLK_SEL)
Use this register to specify whether the system clock has single-ended input or
differential input.
Address:
0h base + 8h offset = 8h
Bit 0 1 2 3
Read
SYSCLK_IN_SEL Reserved
Write
Reset
0* 0* 0* 0*
Bit
4 5 6 7
Read
Reserved
Write
Reset
0* 0* 0* 0*
* Notes:
The register reset value is controlled by SW5[2].•
CPLD_SYSCLK_SEL field descriptions
Field Description
0
SYSCLK_IN_
SEL
System clock input selection
0 System clock differential input (default value)
1 System clock single-ended input
1–7
-
This field is reserved.
Chapter 6 CPLD Programming
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 57