NXP Semiconductors QorIQ LS1043ARDB - CPLD Major Version Register (CPLD_VER); CPLD Minor Version Register (CPLD_VER_SUB)

CPLD memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
F
TDM riser card presence detection register
(CPLD_TDMR_PRS_N)
8 R 01h 6.1.15/61
10 RTC clock assignment register (CPLD_REG_RTC) 8 R/W 00h 6.1.16/61
11 EVDD control register (CPLD_EVDD_SEL) 8 R/W 00h 6.1.17/62
12
CPLD register override physical switch SDHC_VS/SPI_CS0
enable register (CPLD_SOFT_VS_SPICS0)
8 R/W 00h 6.1.18/62
13
SDHC_VS or SPI_CS0 selection register
(CPLD_VS_SPICS0_SEL)
8 R/W See section 6.1.19/63
6.1.1 CPLD major version register (CPLD_VER)
Use this register to specify CPLD major version.
Address:
0h base + 0h offset = 0h
Bit 0 1 2 3 4 5 6 7
Read VER
Reserved
Write
Reset
0 0 0 0 0 0 1 0
CPLD_VER field descriptions
Field Description
0–3
VER
CPLD major version
4–7
-
This field is reserved.
6.1.2 CPLD minor version register (CPLD_VER_SUB)
Use this register to specify CPLD minor version.
Address:
0h base + 1h offset = 1h
Bit 0 1 2 3 4 5 6 7
Read VER_SUB
Reserved
Write
Reset
0 0 0 0 0 0 0 0
CPLD memory map / register definitions
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
52 NXP Semiconductors