• VR500 SW3 generates GVDD up to 2.5 A at a default 1.2 V output for the LS1043A
DDR controllers (GVDD) and all SDRAM GVDD supplies.
• VR500 SW4 generates VTT up to 1 A, and it is 50% of SW3 GVDD voltage as
VTT. An LDO voltage regulator of VR500 generates 50% of GVDD voltage as
VREF.
3.6 POVDD supply
J12 and J13 connectors on the LS1043ARDB connect POVDD power line to LS1043A
PROG_MTR and PROG_SFP pins. Otherwise, they are pulled down to the ground plane.
POVDD supply
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
42 NXP Semiconductors
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