NXP Semiconductors QorIQ LS1043ARDB - I2 C Interface Scheme

LS1043A
USB1_TX/RX, UDP/UDM
USB1
Mini-PCIe
USB2
USB3
USB2_TX/RX, UDP/UDM
USB3_UDP/UDM
USB_DRVVBUS
USB_PWRFAULT
NX5P3090
+5_0V
USB1_P1_PWR
CPLD
USB1PWR_FLT_B
USB1_PWRFAULT_IN
USB1_DRVVBUS
USB2_DRVVBUS
USB2_PWRFAULT
NX5P3090
+5_0V
USB2_P2_PWR
CPLD
USB2PWR_FLT_B
USB2_PWRFAULT
USB2_DRVVBUS
USB1 data bus
USB2 data bus
USB3 data bus
USB2_VBUS
USB1_VBUS
USB3_VBUS
J2 (lower part)
J2 (upper part)
Figure 2-9. USB architecture
2.7
I2C interface
Although the LS1043A processor has up to four I2C buses, most of them are multiplexed
pins. To simplify the circuit and save many mux/demux parts, LS1043ARDB attach all
devices to I2C1 port.
The LS1043ARDB I2C has the following features:
• LS1043A I2C1 is attached to all local devices on the LS1043ARDB.
• I2C1 is also connected to the PCIe and mini-PCIe connectors. The slave address
depends on the PCIe cards.
• LS1043A I2C2, I2C3, and I2C4 are not used as I2C but they are used as other
multiplexed pin functions.
The figure below shows the overall I2C scheme connections.
Chapter 2 Interfaces
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 29