NXP Semiconductors QorIQ LS1043ARDB - UART1 Output Selection Register; SerDes PLL1 Reference Clock Input Selection

6.1.10 UART1 output selection register (CPLD_UART_SEL)
Use this register to specify output for UART1.
Address: 0h base + 9h offset = 9h
Bit 0 1 2 3 4 5 6 7
Read
UART1_
OUT_SEL
Reserved
Write
Reset
0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
The register reset value is controlled by SW3[3].•
CPLD_UART_SEL field descriptions
Field Description
0
UART1_OUT_
SEL
UART1 output selection
0 RJ45
1 CMSIS-DAP (default value)
1–7
-
This field is reserved.
6.1.11 SerDes PLL1 reference clock input selection register
(CPLD_SD1REFCLK_SEL)
Use this register to specify input for the SerDes PLL1 reference clock.
Address:
0h base + Ah offset = Ah
Bit 0 1 2 3
Read
SD1REFCLK_SEL Reserved
Write
Reset
0* 0* 0* 0*
Bit
4 5 6 7
Read
Reserved
Write
Reset
0* 0* 0* 0*
* Notes:
The register reset value is controlled by SW3[4].•
CPLD memory map / register definitions
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
58 NXP Semiconductors