NXP Semiconductors QorIQ LS1043ARDB - LS1043 ARDB Reset Architecture

Table 3-3. Reset configuration input signals (continued)
Configuration signal Pin location DIP switch preset Description
CFG_RCW_SRC7 IFC_AD14 SW4[8] Specifies RCW fetch location
CFG_RCW_SRC8 IFC_AD15 SW5[1] Specifies RCW fetch location
CFG_ENG_USE0 IFC_WE_0_B SW5[2] Selects differential or single-ended
system clock
CFG_ENG_USE1 IFC_OE_B
CFG_ENG_USE2 IFC_WP_0_B
CFG_TEST_SEL TEST_SEL_B SW5[3]
CFG_SOC_USE ASLEEP Pullup
CFG_DRAM_TYPE IFC_A21 Power down by R376 Specifies DRAM type
3.4.2 Reset architecture
The reset signals sent to and received from the LS1043A processor and other devices on
the LS1043ARDB are managed by the CPLD controller.
The figure below shows the LS1043ARDB reset architecture.
Power-on reset
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
40 NXP Semiconductors