LS1043A
AQR105-B1
CPLD
IFC_AD[0:
15]
Reserved
IDT clock generator
(6V49205)
DIFF_SYSCLK
100 MHz
SYSCLK 100 MHz
DDRCLK
100 MHz
25 MHz
SD1_REF_CLK2
100 MHz
100 MHz
CLK
SEL
SD1_REF_CLK1
Mini-PCIe
connector
PCIe slot
PCIE_CLK
MPCIE_CLK
100 MHz
100 MHz
RTC
32.768 kHz
32.768 kHz
32.768 kHz
RGMII2
RGMII1
50 MHz
F104S8A
125 MHz
25 MHz
25 MHz
25 MHz
156.25 MHz
831724KILFT
LVDS
osc.
Figure 4-1. Clocking scheme
4.2
Clock frequency selection
In the LS1043ARDB, the default system clock is supplied by the 100 MHz differential
system clock. It also supports single-ended clock source for SYSCLK and DDRCLK.
Both the differential and single-ended system clocks are provided by an IDT
6V49205BNLGI device, which is a programmable frequency synthesizer with hardware
presets. The device is configured such that it generates as output 100 MHz SYSCLK, 100
MHz DDRCLK, and 100 MHz differential system clock.
The table below shows how to select SYSCLK frequency based on the settings of the
SW3 switch.
Table 4-1. SYSCLK frequency selection
SW3[1] SW3[2] Selected SYSCLK frequency
0 0 66.67 MHz
0 1 100.00 MHz (default value)
1 0 80.00 MHz
Table continues on the next page...
Clock frequency selection
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
44 NXP Semiconductors
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