NXP Semiconductors QorIQ LS1043ARDB - SDHC_VS or SPI_CS0 Selection Register

CPLD_SOFT_VS_SPICS0 field descriptions
Field Description
0
VS_SPICS0_EN
SDHC_VS or SPI_CS0 CPLD register control enable
0 SDHC_VS or SPI_CS0 CPLD register control disable (default value)
1 SDHC_VS or SPI_CS0 CPLD register control enable
1–7
-
This field is reserved.
6.1.19 SDHC_VS or SPI_CS0 selection register
(CPLD_VS_SPICS0_SEL)
Use this register to select SDHC_VS or SPI_CS0.
Address:
0h base + 13h offset = 13h
Bit 0 1 2 3
Read
VS_SPICS0_SEL Reserved
Write
Reset
0* 0* 0* 0*
Bit
4 5 6 7
Read
Reserved
Write
Reset
0* 0* 0* 0*
* Notes:
The register reset value is controlled by SW3[8].•
CPLD_VS_SPICS0_SEL field descriptions
Field Description
0
VS_SPICS0_SEL
SDHC_VS or SPI_CS0 CPLD selection
0 SDHC_VS (default value)
1 SPI_CS0
1–7
-
This field is reserved.
Chapter 6 CPLD Programming
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 63