Table 3-1. CPLD memory map
Address Chip select Bank size Device Data width Access
0x7FB00000 -
0x7FB0FFFF
CS2 64 KB CPLD 8 bits Read/write
For details on the CPLD registers, see CPLD Programming.
3.4 Power-on reset
The figure below shows a timing diagram of the power-on reset (POR) sequence.
PORESET_B
HRESET_B
RESET_REQ_B
ASLEEP
SYSCLK
POR configs
(High impedance)
(High impedance)
Figure 3-3. POR sequence
NOTE
Reset configuration input signals are only sampled at the
negation of POR. Reset configuration input pins, such as
CFG_RCW_SRC[0:8], CFG_GPINPUT[0:7],
CFG_ENG_USE[0:2], and CFG_DRAM_TYPE function
differently when the device is not in the Reset state.
The LS1043A control group signals are basically used to stop or restart an execution.
PORESET_B indicates the power-on reset input signal. Use it for reset assertion.
HRESET_B indicates the hard reset input signal. It is a bi-directional open drain signal. It
functions as an output signal during initial steps in the POR sequence.
The table below describes the POR sequence.
Power-on reset
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
38 NXP Semiconductors
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