NXP Semiconductors QorIQ LS1043ARDB - POR RCW Source Location Register 1

CPLD_SOFT_MUX_ON field descriptions (continued)
Field Description
4
TDMCLK_
SDHC_USB_IF_
CTRL_EN
TDM CLK or SDHC/USB interface control enable
0 TDM CLK or SDHC/USB interface control disable (default value)
1 TDM CLK or SDHC/USB interface control enable
5
SDHC_SPICS_
IF_CTRL_EN
SDHC or SPI_CS interface control enable
0 SDHC or SPI_CS interface control disable (default value)
1 SDHC or SPI_CS interface control enable
6
FLASH_BANK_
CTRL_EN
Flash bank control enable
0 Flash bank control disable (default value)
1 Flash bank control enable
7
EVDD_CTRL_EN
EVDD voltage control enable
0 EVDD select disable (default value)
1 EVDD select enable
6.1.6 POR RCW source location register 1
(CPLD_REG_RCW_SRC1)
Use this register to configure RCW source bits 0-7.
Address:
0h base + 5h offset = 5h
Bit 0 1 2 3 4 5 6 7
Read
CFG_RCW_SRC[0:7]
Write
Reset
0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
The register reset value is controlled by SW4[1] - SW4[8].•
CPLD_REG_RCW_SRC1 field descriptions
Field Description
0–7
CFG_RCW_
SRC[0:7]
POR RCW source location
Chapter 6 CPLD Programming
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 55