Chapter 2
Interfaces
The LS1043ARDB architecture is primarily determined by the LS1043A processor with
the need to evaluate LS1043A processor features and to test its ability to deliver an easily
usable off-the-shelf software development platform. Following are the main interfaces
that form the LS1043ARDB architecture:
• DDR interface
• IFC interface
• Serial interfaces
• Ethernet interface
• SerDes interface
• USB interface
• I2C interface
2.1
DDR interface
The LS1043ARDB supports high-speed DRAM with 2 GB double data rate 4 (DDR4)
SDRAM discrete devices (32-bit bus). The memory interface includes all necessary
termination and I/O powers. It is routed such that maximum performance of the memory
bus can be achieved. The figure below shows the DDR memory architecture.
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 17
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