NXP Semiconductors QorIQ LS1043ARDB - EVDD Control Register; CPLD Override Switches Enable Register

CPLD_REG_RTC field descriptions (continued)
Field Description
1–7
-
This field is reserved.
6.1.17 EVDD control register (CPLD_EVDD_SEL)
Use this register to control the EVDD voltage.
Address:
0h base + 11h offset = 11h
Bit 0 1 2 3 4 5 6 7
Read
EVDD_SEL Reserved
Write
Reset
0 0 0 0 0 0 0 0
CPLD_EVDD_SEL field descriptions
Field Description
0
EVDD_SEL
EVDD voltage select register
0 3.3 V (default value)
1 1.8 V
1–7
-
This field is reserved.
6.1.18 CPLD register override physical switch SDHC_VS/
SPI_CS0 enable register (CPLD_SOFT_VS_SPICS0)
Use this register to enable CPLD register value override physical switch to select
SDHC_VS or SPI_CS0.
Address:
0h base + 12h offset = 12h
Bit 0 1 2 3
Read
VS_SPICS0_EN Reserved
Write
Reset
0 0 0 0
Bit
4 5 6 7
Read
Reserved
Write
Reset
0 0 0 0
CPLD memory map / register definitions
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
62 NXP Semiconductors