LS1043A
NOR
(MT28EW01G)
IFC_AD[0:15]
NAND
(MT29F4G08ABB
DAH4)
IFC_ADDR[16:27]
IFC_AD[0:7]
IFC
CPLD
NOR_CS_B
NOR_RB_B
NAND_CS_B
NAND_RB_B
IFC_CLE
IFC_AD[0:15]
IFC_CS[0:3]_B
IFC_WE_B, IFC_OE_B, IFC_AVD
IFC_CLE, IFC_TE, IFC_CLK0
IFC_RB[0:1]_B
Figure 2-2. IFC block diagram
LS1043ARDB uses a combination of the IFC chip select signals and DIP switches to
allow dynamic reconfiguration of the IFC boot device (which addresses IFC_CS_B[0]
only).
The table below summarizes the IFC chip select routing.
Table 2-1. IFC chip select device mapping
SW4[1:8]+SW5[1]= Chip select Memory Data width
000100101 CS0 NOR flash 16 bits
CS1 NAND flash 8 bits
CS2 CPLD registers 8 bits
100000110 CS0 NAND flash 8 bits
CS1 NOR flash 16 bits
CS2 CPLD registers 8 bits
Chapter 2 Interfaces
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 19
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