NXP Semiconductors QorIQ LS1043ARDB - CPLD Override Switches Enable Register

CPLD_SYSTEM_RST field descriptions (continued)
Field Description
0 System is running (default value)
1 System is reset
1–7
-
This field is reserved.
6.1.5 CPLD override physical switches enable register
(CPLD_SOFT_MUX_ON)
Use this register to specify whether or not a CPLD override physical switch is enabled.
Address:
0h base + 4h offset = 4h
Bit 0 1 2 3
Read
RCW_SRC_LOC_
CTRL_EN
SYSCLK_IN_CTRL_EN
UART1_OUT_CTRL_
EN
SD1REFCLK_IN_
CTRL_EN
Write
Reset
0 0 0 0
Bit
4 5 6 7
Read
TDMCLK_SDHC_USB_
IF_CTRL_EN
SDHC_SPICS_IF_
CTRL_EN
FLASH_BANK_CTRL_
EN
EVDD_CTRL_EN
Write
Reset
0 0 0 0
CPLD_SOFT_MUX_ON field descriptions
Field Description
0
RCW_SRC_
LOC_CTRL_EN
RCW source location control enable
0 RCW source location control disable (default value)
1 RCW source location control enable
1
SYSCLK_IN_
CTRL_EN
System clock single-ended or differential input control enable
0 System clock single-ended or differential input control disable (default value)
1 System clock single-ended or differential input control enable
2
UART1_OUT_
CTRL_EN
UART1 output control enable
0 UART1 output control disable (default value)
1 UART1 output control enable
3
SD1REFCLK_
IN_CTRL_EN
SerDes PLL1 reference clock input control enable
0 SerDes PLL1 reference clock input control disable (default value)
1 SerDes PLL1 reference clock input control enable
Table continues on the next page...
CPLD memory map / register definitions
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
54 NXP Semiconductors