Table 10. JTAG and SWD signal description (continued)
JTAG mode SWD mode Description MCU port Recommendation
—
SWCLK Serial Wire Debug clock PIO0_11 Input, Pull-Down
—
SWDIO Serial Wire Debug I/O PIO0_12 Input, Pull-Up
RESET RESET Reset MCU Dedicate Pin Pull-Up
GND GND Ground Dedicate Pins
—
External pull up/down resistors for the JTAG signals can be added in order to increase debugger
connection robustness.
NOTE
Figure 7. SWD connector connections
NXP Semiconductors
Debug and programing interface
Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020
Application Note 13 / 24
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