Ocean Optics Flame-S - Page 111

8: Firmware and Advanced Communications
225-00000-000-11-201604 101
program needs to delay for this length of time before issuing another command. In some
instances, other commands will also write to these registers (i.e., integration time), in these
cases the user has the options of setting the parameters through 2 different methods.
Byte Format
Byte 0
Byte 1
Byte 2
Byte 3
0x6A
Register Value
Data Byte LSB
Data Byte MSB
Register
Address
Description
Default
Value
Min
Value
Max Value
Time Base
0x00
*
Master Clock Counter
Divisor
24
1
0xFFFF
48MHz
0x04
FPGA Firmware
Version (Read Only)
0x08
Continuous Strobe
Timer Interval Divisor
48000
0
0xFFFF
Continuous
Strobe Base
Clock
(see Register
0x0C)
0x0C
Continuous Strobe
Base Clock Divisor
4800
0
0xFFFF
48MHz
0x10
*
Integration Period
Base Clock Divisor
480
0
0xFFFF
48MHz
0x14
Set base_clk or
base_clkx2
0: base_clk
1: base_clkx2
0
0
1
N/A
0x18
*
Integration Clock
Timer Divisor
600
0
0xFFFF
Integration
Period Base
Clock
(see Register
0x10)
0x20
Reserved