Ocean Optics Flame-S - Page 112

8: Firmware and Advanced Communications
102 225-00000-000-11-201604
Register
Address
Description
Default
Value
Min
Value
Max Value
Time Base
0x28
Hardware Trigger
Delay – Number of
Master Clock cycles
to delay when in
External Hardware
Trigger mode before
the start of the
integration period
0
0
0xFFFF
2MHz
0x2C
&*
Trigger Mode
0 = Free Running
1 = External
Synchronization
2 = External
Hardware Trigger
0
0
2
N/A
0x30
Reserved
0x38
Single Strobe High
Clock Transition
Delay Count
1
0
0xFFFF
2MHz
0x3C
Single Strobe Low
Clock Transition
Delay Count
5
0
0xFFFF
2MHz
0x40
Lamp Enable
0
0
1
N/A
0x48
GPIO Mux Register
0: pin is GPIO pin
1: pin is alternate
function
0
0
0x03FF
N/A
0x50
GPIO Output Enable
1: pin is output
0: pin is input
0
0
0x03FF
N/A
0x54
GPIO Data Register
For Output: Write
value of signal
For Input: Read
current GPIO state
0
0
0x03FF
N/A
0x58
Reserved
0x5C
Reserved
0x74
Offset Value
0
0
0xFFFF
N/A