8: Firmware and Advanced Communications
225-00000-000-11-201604 77
Master Clock Counter Divisor
FPGA Firmware Version (Read Only)
Continuous Strobe Timer Interval Divisor
Continuous
Strobe Base
Clock
(see Register
0x0C)
Continuous Strobe Base Clock Divisor
Continuous Strobe LSB Register
Integration Period Base Clock Divisor
Integration Period LSB Register
Set base_clk or base_clkx2
0: base_clk
1: base_clkx2
Integration Clock Timer Divisor
Integration
Period Base
Clock
(see Register
0x10)
Integration Period MSB Register
Hardware Trigger Delay – Number of Master
Clock cycles to delay when in External
Hardware Trigger mode before the start of the
integration period
Hardware Trigger Delay – Delay the start of
integration from the rising edge of the trigger in
500ns increments
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