Pin No. Mark I/O Function
1 DRVDD I Power supply for
DRAM interface (Pin
2 to 19 and 80)
2 D0 I/O DRAM data I/O signal
0
3 D1 I/O DRAM data I/O signal
1
4 NWE O DRAM write enable
signal
5 NRAS O DRAM RAS control
signal
6 D2 I/O DRAM data I/O signal
2
7 D3 I/O DRAM data I/O signal
3
8 NCAS0 O DRAM CAS control
signal 0
9 A10
(NCAS1)
O DRAM CAS control
signal 10
10 A8 O DRAM address signal
8
11 A7 O DRAM address signal
7
12 A6 O DRAM address signal
6
13 A5 O DRAM address signal
5
14 A4 O DRAM address signal
4
15 A9 O DRAM address signal
9
16 A0 O DRAM address signal
0
17 A1 O DRAM address signal
1
87