Philips 32PFL5605D/78 - Page 34

Circuit Descriptions
EN 34 LC9.3L LA7.
2010-Mar-26
7.6 I
2
C
Refer to Figure 7-8 for the I
2
C architecture.
Figure 7-8 I
2
C architecture
7.7 TCON
The Timing Controller is integrated in the SSB (“Forward
Integration” concept). Refer to Figure 7-9
for the TCON system
block diagram.
Figure 7-9 TCON system block diagram
18970_207_100325.eps
100325
MT5392
NVM
7605
10k
+3V3_SW
10k
22R
22R
OSDA0 (J30)
OSCL0 (J29)
SDA-MAIN
SCL-MAIN
Ambilight
μController
7801
100R
100R
4k7
+3V3_SW
4k7
47
48
AMBI_ SDA
AMBI_ SCL
OSDA1 (K30)
OSCL1 (K29)
HDMIMUX
7900
22R
DDC_SCL
DDC_SDA
OSDA2 (AJ10)
OSCL2 (AK10)
67
68
40
27
100R
ForDebugging
100R
10K
10K
+3V3_SW
4k7
+3V3_SW
4k7
1R
1R
TUNER_SDA
TUNER_SCL
100R
FRONTEND_SDA
FRONTEND_SCL
100R
15p
15p
TUNER
1205
12
13
L28
L29
47p
5
6
10p
10p
18920_209_100318.eps
100319
EEPROM
TFT – LCD Panel
Mini - LVDS
Control
Signals
+3V3
+1V2
VGH (+35V)
VGL ( − 6V)
+12V
LVDS
(10bit)
Timing
Controller
Power
Block
Gamma
Reference
Voltage
Source Drive IC
Gate Drive IC
MTK
LCD Panel
TCONMain Platform
SSB
+ 15.6V