Quectel M10

M10 Hardware Design
Table 31: M10 Connection diagrams
PIN NO. PIN NAME I/O PIN NO. PIN NAME I/O
1 DISP_DATA I/O 2 DISP_CLK O
3 DISP_CS O 4 DISP_D/C O
5 DISP_RST O 6 NETLIGHT O
7 VDD_EXT O 8 GND1
9 DBG_RXD I 10 DBG_TXD O
11 SIM_PRESENCE I 12 SIM_VDD O
13 SIM_DATA I/O 14 SIM_CLK O
15 SIM_RST O 16 VRTC I/O
17 EMERG_OFF I 18 PWRKEY I
19 AGND O 20 SPK2P O
21 SPK1N O 22 SPK1P O
23 MIC1P I 24 MIC1N I
25 MIC2P I 26 MIC2N I
27 LIGHT_MOS O 28 KBR0 O
29 KBR1 O 30 KBR2 O
31 KBR3 O 32 KBR4 O
33 KBC0 I 34 KBC1 I
35 KBC2 I 36 KBC3 I
37 KBC4 I 38 GPIO1_KBC5 I/O
39 BUZZER O 40 TEMP_BAT I
41 ADC0 I 42 GND2
43 RF_ANT I/O 44 GND3
45 GND4 46 GND5
47 GND6 48 GND7
49 GND8 50 VBAT1 I
51 VBAT2 I 52 VBAT3 I
53 Reserve 54 Reserve
55 RI O 56 DCD O
57 CTS O 58 RTS I
59 DTR I 60 TXD O
61 RXD I 62 Reserve
63 Reserve 64 GPIO0 I/O
M10_HD_V1.00 - 58 -
Quectel