Quectel QuecOpen AG525R-GL

Automotive Module Series
AG525R-GL QuecOpen
Hardware Design
AG525R-GL_QuecOpen_Hardware_Design 8 / 104
Figure Index
Figure 1: Functional Diagram for AG525R-GL QuecOpen
®
..................................................................... 20
Figure 2: Pin Assignment (Top View) ....................................................................................................... 22
Figure 3: Sleep Mode Current Consumption Diagram ............................................................................. 40
Figure 4: Sleep Mode Application with USB Remote Wakeup ................................................................. 40
Figure 5: Sleep Mode Application without USB Remote Wakeup ............................................................ 41
Figure 6: Sleep Mode Application without Suspend Function .................................................................. 42
Figure 7: Power Supply Limits during Burst Transmission ...................................................................... 43
Figure 8: VBAT Reference Design .......................................................................................................... 44
Figure 9: 12/24 V Power Supply System Reference Design ................................................................... 44
Figure 10: Turn on the Module Using Driving Circuit ............................................................................... 45
Figure 11: Turn on the Module Using Keystroke ...................................................................................... 46
Figure 12: Power-on Timing .................................................................................................................... 46
Figure 13: Turn on the Module using PON_1 .......................................................................................... 47
Figure 14: Power-off Timing .................................................................................................................... 48
Figure 15: Reference Circuit of RESET by Using Driving Circuit ............................................................. 49
Figure 16: Reference Circuit of RESET by Using Button ........................................................................ 49
Figure 17: Timing of Resetting Module .................................................................................................... 50
Figure 18: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector ........................ 51
Figure 19: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector .......................... 51
Figure 20: Reference Circuit of USB 2.0 Application ............................................................................... 53
Figure 21: Reference Circuit of USB 3.0 Application ...........................................................................
.... 53
Figure 22: Reference Circuit with Translator Chip ................................................................................... 56
Figure 23: Reference Circuit with Transistor Circuit ................................................................................ 56
Figure 24: Reference Circuit of I2S and I2C Application with Audio Codec ............................................. 57
Figure 25: Reference Design of SDIO Interface for eMMC Application ................................................... 59
Figure 26: SPI Timing .............................................................................................................................. 60
Figure 27: Simplified Block Diagram for Ethernet Application ................................................................. 62
Figure 28: Reference Circuit of RGMII Interface with PHY Application ................................................... 63
Figure 29: Reference Circuit for Connection with WLAN&BT PHY ......................................................... 66
Figure 30: Reference Circuit of USB_BOOT Interface ............................................................................ 68
Figure 31: Reference Circuit of RF Antenna Interfaces ........................................................................... 72
Figure 32: Microstrip Design on a 2-layer PCB ....................................................................................... 73
Figure 33: Coplanar Waveguide Design on a 2-layer PCB ...................................................................... 73
Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) ................... 74
Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) ................... 74
Figure 36: Description of the HFM Connector ......................................................................................... 76
Figure 37: Referenced Heatsink Design (Heatsink at the Top of the Module) ......................................... 89
Figure 38: Referenced Heatsink Design (Heatsink at the Backside of Customers’ PCB) ........................ 90
Figure 39: Module Top and Side Dimensions .......................................................................................... 91
Figure 40: Module Bottom Dimensions (Top View) .................................................................................. 92
Figure 41: Recommended Footprint (Top View) ...................................................................................
... 93