Quectel RG255C-GL - Page 28

5G Module Series
RG255C-GL_Mini_PCIe_Hardware_Design 27 / 57
The following table shows the pin definition of PCM and I2C interfaces that can be applied in audio codec
design.
Table 11: Pin Definition of PCM and I2C Interfaces
In primary mode, data is sampled on the falling edge of PCM_CLK and transmitted on the rising edge.
The PCM_SYNC falling edge represents the MSB. In this mode, PCM_CLK supports 256 kHz, 512 kHz,
1024 kHz and 2048 kHz when PCM_SYNC operates at 8 kHz, and also supports 4096 kHz when
PCM_SYNC operates at 16 kHz.
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
MSB
1 2 256255
PCM_DIN
MSB
LSBMSB
125 μs
Figure 9: Timing in Primary Mode
In auxiliary mode, data is also sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. But in this mode, the PCM_SYNC rising edge represents the MSB. PCM_CLK supports 256 kHz,
512 kHz, 1024 kHz and 2048 kHz when PCM_SYNC reaches 8 kHz with a 50 % duty cycle.
Pin Name
Pin No.
I/O
Description
Comment
PCM_CLK
45
DIO
PCM clock
1.8 V power domain.
PCM_DOUT
47
DO
PCM data output
PCM_DIN
49
DI
PCM data input
PCM_SYNC
51
DIO
PCM data frame sync
I2C_SCL
30
DO
I2C serial clock
(for external codec)
Requires external pull-up to 1.8 V.
I2C_SDA
32
DIO
I2C serial data
(for external codec)