Quectel RG255C-GL - Page 29

5G Module Series
RG255C-GL_Mini_PCIe_Hardware_Design 28 / 57
The following figure shows the timing relationship in auxiliary mode with 8 kHz PCM_SYNC and 256 kHz
PCM_CLK.
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
PCM_DIN
MSB
1 2
3231
LSB
125 μs
Figure 10: Timing in Auxiliary Mode
The clock and mode of PCM can be configured by AT+QDAI, and the default configuration is short frame
mode (master mode, PCM_CLK = 2048 kHz, PCM_SYNC = 8 kHz, 16-bit linear data format). In addition,
RG255C-GL Mini PCIe’s firmware has integrated the configuration on some PCM codec’s application with
I2C interface. See document [3] for details about AT+QDAI.
The following figure shows a reference design of PCM and I2C interfaces with an external codec IC.
PCM_DIN
PCM_DOUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
Codec
Module
2.2K 2.2K
BCLK
FS
DACIN
ADCOUT
SCLK
SDIN
BIAS
MIC_BIAS
MIC+
MIC-
SPKOUT+
SPKOUT-
1.8 V
Figure 11: Reference Circuit of PCM and I2C Application with Audio Codec