Sanyo PLV-80 - LCD Panel Driving Stage

-47-
GO[0-9] RO[0-9]
2,3
1 2
4
15
9,1
0
4
15
38
159, 64
5, 6
230
47142
231 237
PW_DCLK PW_DVSYNC PW_DHSYNC
IC4401
<EP1S25F672>
FPGA
IC1305
FLASH
MEMOR
Y
IC302
EEPROM
IC3411
SDRAM
IC801
<HD6417727>
CPU
IC1501
<M62399>
DA
C
IC1601
<TC4053>
SW
PW_DRE[0-9] PW_DGE[0-9] PW_DBE[0-9]
73
14
3
142
260 175 259
29, 27, 26
21,94,9
3
46,16
3
133, 135, 136
214, 215
FPGA_CLKO
TPNRSB
B_NRS
G_NRS
R_NRS
TPNRSA
V1/REF
SCLK_GAM
SDATA_GAM
STB_GAM
FPGA_VOUT FPGA_HOUT
RO
UT[0-9]
GOUT[0-9] BOUT[0-9]
SC_A SC_D
IC1301 IC1311 IC1321 IC1331
DDR
MEMOR
Y
IC301
<PW388>
SCAN
CONVERTER
CPU_SDA_3V
CPU_SCL_3V
SH_SDA_3V
SH_SCL_3V
FRPG
FRPR
IC401
<L3E07090>
DIGITAL
GAMMA
CORRECTION
IC6751
<SN74LVC16244>
IC501
<L3E06110>
B-S&H
IC531
<L3E06110>
G-S&H
IC561
<L3E06110>
R-S&H
BO[0-9]
TP35B
TP35G
R-LCD
PANE
L
TP35R
B-LCD
PANEL
G-LCD
PANEL
MAIN
Chassis Description
LCD panel driving stage