HIGH HIGH HIGH Interrupt Acknowledge
3.17 System Control inputs are used to either reset or halt the processor and to indicate to the processor that bus errors have occurred. There are
three system control signals: BERR, HALT and RESET.
3.18 BERR (Bus Error). Not used on the QL.
3.19 RESET and HALT. The bidirectional RESET signal line acts to reset (start a system initialisation sequence) the processor in response to an
external RESET signal. An internally generated reset (result of a reset instruction) causes all external devices to be reset and the internal state of
the processor is not affected. A total system reset (processor and external devices) is the result of external HALT and RESET signals applied at
the same time. HALT and RESET are tied together on the QL.
4. INTEL 8049 INTELLIGENT PERIPHERAL CONTROLLER (IPC)
4.1 The 8049, IC24, is a totally self-sufficient 8-bit single chip microcomputer containing 2 k bytes of program memory and 128 bytes of RAM. It is
clocked internally at 11 MHz from crystal X4.
4.2 In this application the function of the 8049 is to:
1. receive RS232 interface signals,
2. monitor the keyboard,
3. control the loudspeaker,
4. control the joystick.
The IPC utilises a data bus, two 8-bit I/O ports and some control lines to control these functions.
4.3 Data Bus. DB0-DB7 constitutes an 8-bit bi-directional data bus with active high tri-state input/outputs. It is used only as input for scanning the
keyboard and joysticks.
4.4 Control Bus. Control is exercised by a number of discrete signals which organise the direction and flow of data between the 8049 and the
ZX8302, and also communicate with, and monitor, other areas of the QL.
4.5 Control Lines. The role of each control line is as follows:
1. T1. Timer/Counter Input, 4 times the baud rate set by the user, controlled by a ZX8302 register.
2. WR. Output strobe, active low, used as a read or write strobe to enable keyboard, joystick or RS232 data to IC23 over the P27 link line.
3. P10-P17. Output lines used to scan the keyboard and joysticks in conjunction with DB0-DB7.
4. P26. Not used on QL.
5. P21. Loudspeaker output.
6. P27. Serial link transmitting data to IC23.
7. P24, P25. RS232 handshake lines.
8. RESET. Input from IC23 used to initialise the 8049.
9. CLKCPU. Clock input from ZX8301.
10. P23, P22 (IPL1, IPL2). Interrupt request lines to 68008 CPU.
11. INT, P20. Interrupt input. INT initiates an interrupt on reception of RS232 first transition. P20 is used to read the data on the RS232 receive
lines.
4.6 RS232 Link. IC24 is responsible for the receive side of the RS232 serial data link only, and IC23 the transmit side. Since, the RS232 link is
best understood as an entity both aspects are discussed here.
4.7 J5 and J6 are two RS232 connectors. J6 is connected so that the device connected to it may act as the Data Terminal Equipment (DTE) which
originates the Data Terminal Ready (DTR) signal. J5 connects to the Data Communications Equipment (DCE) i.e. the local QL assumes DTE
status. Figure 1.1 illustrates this schematically.
4.8 The RS232 interface uses an 11-bit ASCII data frame, viz. one start bit, eight data bits and two stop bits comprise one character. Two stop bits
are always sent but the interface receives compatibly with one except at 9600 baud, where one and a half stop bits are required. Data is
transmitted asynchronously in the full duplex mode.
4.9 Consider the QL as the DTE. Both DTE and DCE are switched on and have their DTR signals asserted. CTS and DTR (Clear to Send, Data
Terminal Ready) do not form a handshake pair but are similar signals going in opposite directions. Serial data is transmitted by IC23 via driver
IC25/6 and received by line receiver IC26/11. From IC26/11 data is fed to NAND gate IC27/9, pin 10 of which is set to the high state by the
program, and input to IC24 pins 6 and 21 via IC27/11.
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