VDD
VDDA
3
SDA/SDIO
A1/SDO
SCLK
A0/CS
I2C_SEL
SPI/
I
2
C
NVM
RST
Zero Delay
Mode
FB_IN
FB_IN
OE
Si5341
Generator
Clock
÷R
0
÷R
2
÷R
3
÷R
4
÷R
5
÷R
6
÷R
7
÷R
8
÷R
9
÷R
1
OUT0
VDDO0
OUT0
OUT2
VDDO2
OUT2
OUT3
VDDO3
OUT3
OUT4
VDDO4
OUT4
OUT5
VDDO5
OUT5
OUT6
VDDO6
OUT6
OUT7
VDDO7
OUT7
OUT8
VDDO8
OUT8
OUT9
VDDO9
OUT9
OUT1
VDDO1
OUT1
÷P
fb
LPF
PD
÷
M
n
M
d
PLL
IN_SEL[1:0]
XA
XB
25MHz, 48-
54MHz
XTAL
OSC
÷P
2
÷P
1
÷P
0
IN0
IN0
IN1
IN1
IN2
IN2
FDEC
FINC
Frequency
Control
÷
N
0n
N
0d
t
0
÷
N
2n
N
2d
÷
N
3n
N
3d
÷
N
4n
N
4d
t
2
t
3
t
4
÷
N
1n
N
1d
t
1
MultiSynth
SYNC
Dividers/
Drivers
Status
Monitors
LOL
INTR
÷Pxaxb
Figure 2.1. Si5341 Detailed Block Diagram
Si5341, Si5340 Rev D Family Reference Manual • Functional Description
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
10 Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 10
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