14.3.3 Page 2 Registers Si5340
Table 14.140. 0x0202-0x0205 XAXB Frequency Adjust
Reg Address Bit Field Type Setting Name Description
0x0202 7:0 R/W XAXB_FREQ_OFF-
SET
32 bit 2’s complement offset adjustment
0x0203 15:8 R/W XAXB_FREQ_OFF-
SET
0x0204 23:16 R/W XAXB_FREQ_OFF-
SET
0x0205 31:24 R/W XAXB_FREQ_OFF-
SET
The clock that is present on XAXB pins is used to create an internal frequency reference for the PLL. The XAXB_FREQ_OFFSET
word is added to the M_NUM to shift the VCO frequency to compensate for a crystal that does not have an 8 pf CL specification. The
adjustment range is up to ±1000 ppm.
Table 14.141. 0x0206 PXAXB Divider Value
Reg Address Bit Field Type Setting Name Description
0x0206 1:0 R/W PXAXB Sets the value for the divider on the XAXB input.
• 0 = divider value 1
• 1 = divider value 2
• 2 = divider value 4
• 3 = divider value 8
The following registers configure the P-dividers, which are located at the four input clocks seen in Figure 2.2 Si5340 Detailed Block
Diagram on page 11. ClockBuilder Pro calculates the correct values for the P-dividers.
Table 14.142. 0x0208-0x020D P0 Dividers
Reg Address Bit Field Type Setting Name Description
0x0208 7:0 R/W P0 48-bit Integer Number
0x0209 15:8 R/W P0
0x020A 23:16 R/W P0
0x020B 31:24 R/W P0
0x020C 39:32 R/W P0
0x020D 47:40 R/W P0
Table 14.143. 0x020E-0x0211 P0 Divider Enable/Set
Reg Address Bit Field Type Setting Name Description
0x020E 7:0 R/W P0_SET Set by CBPro
0x020F 15:8 R/W P0_SET
0x0210 23:16 R/W P0_SET
0x0211 31:24 R/W P0_SET
Si5341, Si5340 Rev D Family Reference Manual • Register Map
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