Table 14.61. 0x023B-0x023E M Divider Denominator
Reg Address Bit Field Type Setting Name Description
0x023B 7:0 R/W M_DEN 32-bit Integer Number
0x023C 15:8 R/W M_DEN
0x023D 23:16 R/W M_DEN
0x023E 31:24 R/W M_DEN
The M-divider numerator and denominator is determined by ClockBuilder Pro for a given frequency plan.
Table 14.62. 0x023F M Divider Update Bit
Reg Address Bit Field Type Setting Name Description
0x023F 0 S M_UPDATE Must write a 1 to this bit to cause M divider changes to
take effect.
Bits 7:1 of this register have no function and can be written to any value.
Table 14.63. 0x024A-0x024C R0 Divider
Reg Address Bit Field Type Setting Name Description
0x024A 7:0 R/W R0_REG 24-bit Integer Number. Divide value = (R0_REG+1) x 2
To set R0 = 2, set OUT0_RDIV_FORCE2 = 1, and then
the R0_REG value is irrelevant.
When OUT0_RDIV_FORCE2 = 0, then setting
R0_REG = 0 will disable the divider.
0x024B 15:8 R/W R0_REG
0x024C 23:16 R/W R0_REG
The final output R dividers are even dividers beginning with divide-by-2. While all other values follow the formula in the bit description
above, divide-by-2 requires an extra bit to be set. For divide-by-2, set OUT0_RDIV_FORCE2 = 1. See the description for register bit
0x0108[2] in this register map.
The R1-R9 dividers follow the same format as the R0 divider description above.
Table 14.64. R Dividers for Outputs 1,2,3,4,5,6,7,8,9
Register Address Setting Name Size Same as Address
0x024D-0x024F R1_REG 24-bit Integer Number 0x024A-0x024C
0x0250-0x0252 R2_REG 24-bit Integer Number 0x024A-0x024C
0x0253-0x0255 R3_REG 24-bit Integer Number 0x024A-0x024C
0x0256-0x0258 R4_REG 24-bit Integer Number 0x024A-0x024C
0x0259-0x025B R5_REG 24-bit Integer Number 0x024A-0x024C
0x025C-0x025E R6_REG 24-bit Integer Number 0x024A-0x024C
0x025F-0x0261 R7_REG 24-bit Integer Number 0x024A-0x024C
0x0262-0x0264 R8_REG 24-bit Integer Number 0x024A-0x024C
0x0268-0x026A R9_REG 24-bit Integer Number 0x024A-0x024C
Si5341, Si5340 Rev D Family Reference Manual • Register Map
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