Table 14.73. 0x0317 N1 Divider Update Bit
Reg Address Bit Field Type Setting Name Description
0x0317 0 S N1_UPDATE Must write a 1 to this bit to cause N1 divider changes to
take effect.
Table 14.74. 0x0322 N2 Divider Update Bit
Reg Address Bit Field Type Setting Name Description
0x0322 0 S N2_UPDATE Must write a 1 to this bit to cause N2 divider changes to
take effect.
Table 14.75. 0x032D N3 Divider Update Bit
Reg Address Bit Field Type Setting Name Description
0x032D 0 S N3_UPDATE Must write a 1 to this bit to cause N3 divider changes to
take effect.
Table 14.76. 0x0338 N4 Divider Update Bit
Reg Address Bit Field Type Setting Name Description
0x0338 0 S N4_UPDATE Must write a 1 to this bit to cause N4 divider changes to
take effect.
Table 14.77. 0x0338 All N Dividers Update Bit
Reg Address Bit Field Type Setting Name Description
0x0338 1 S N_UPDATE Writing a 1 to this bit will update all N dividers to the
latest value written to them. A specific N divider that has
not been changed will not be affected by writing a 1 to
this bit. When this bit is written to a 1, all other bits in
this byte should only be written to a 0.
Table 14.78. 0x0339 FINC/FDEC Masks
Reg Address Bit Field Type Setting Name Description
0x0339 4:0 R/W N_FSTEP_MSK 0 to enable FINC/FDEC updates
1 to disable FINC/FDEC updates
• Bit 0 corresponds to MultiSynth N0 N_FSTEP_MSK 0x0339[0]
• Bit 1 corresponds to MultiSynth N1 N_FSTEP_MSK 0x0339[1]
• Bit 2 corresponds to MultiSynth N2 N_FSTEP_MSK 0x0339[2]
• Bit 3 corresponds to MultiSynth N3 N_FSTEP_MSK 0x0339[3]
• Bit 4 corresponds to MultiSynth N4 N_FSTEP_MSK 0x0339[4]
There is one mask bit for each of the five N dividers.
Si5341, Si5340 Rev D Family Reference Manual • Register Map
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