EasyManua.ls Logo

Sony HDVF-C950W - Page 56

Sony HDVF-C950W
84 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
6-2
HDVF-C950W
6-2
OverallOverall
Overall
VF
(20-pin Male)
IC500,501
IC305,314
CONFIG
SDRAM
EPR
ROM
IC200 FL200 IC208 IC214 IC300
Y VIDEO IN
AMP LPF AMP ADC
10
64 12 2
10bit
FPGA 1/2
DATA ADRS CTRL
CLAMP
AMP
30
PI1D[29:0]
SYNC
H_SYNC
PIVS
DISPLAY PROCESSOR
SEP1
PIHS
SYNC
D_SYNC
PIFLD
SEP2
4
PIACT
IC201 FL201 IC209 IC215
74MHz
PICLK
Pb VIDEO IN
AMP LPF AMP ADC
10
74MHz
10bit
IPCLK
IC303 X300
X1.33
CLAMP
PHASE
AMP
FREQ.
VCO
DETECTOR
74MHz
IC202 FL202 IC210 IC216 IC306
Pr VIDEO IN
AMP LPF AMP ADC
10
18MHz
FPCG
10bit
77MHz
331kHz
CLOCK
33.2MHz
CLAMP
GENERATOR
AMP
D304,305
Q300,301
A_CLP
IC400
IIC SCK
SCLK
IIC SDA
IIC
IF
EEPROM
4.64MHz
IC307
18.5MHz
9.25MHz
IC5
UP_TALLY_ENBL_CAM
CPU_CLK
IC600
IC6
LE-317
SW-1299
SW
:
ASSIGN_1
SW
:
ASSIGN_2
IC4
Q4,6,7
S600
4
R TALLY
4bit DIP SW
DRIVER
CPU
(SH7145)
LE-315
S601
7
8bit DIP SW
IC4
Q8-10
G TALLY
Second VF
DRIVER
SW-1298
2
Q11-13
DRIVER
POWER SW
LE-316
TALLY DIMMER HIGH/LOW
FRONT_TALLY_ENBL
UP_TALLY_ENBL
MCLK 77MHz
IC300 IC700
LCD Module
POD[20:0]
30
FPGA 2/2
24
POHS
H SYNC
LVDS
POVS
V SYNC
LVDS
CABLE
POACT
3
DE
TRANS
-MITTER
POCLK
CLK
33.2MHz
OPE
Data Map : A
IC322
IC323
IP_RST IC309
RESET
IC304
RESET_CPU
Reset
2
IC601
Chara_clk
CHAR
2
CHAR
CHAR BACK
1.15MHz
4
GEN
IC606
EEPROM
2
IIC
2
U/D, L/R
BL_ON/OFF
IC614 IC702
1kHz BL_Level V
BRT
3
DAC
Bright_ADJ
UP_TALLY_DIMMER
VR-315
IC9
RE-237
BRIGHT
BRIGHT_ADJ
CONTRAST
PEAKING
UP TALLY DIMMER
PEAKING
CTL
IC11
+5V +3.3V
PR-292
CN14

Related product manuals