Sony RCD-W3 Service Manual

RCD-W3
33 33
5-7.SCHEMATIC DIAGRAM – BD-R SECTION (4/6) –
R501
R502
C523
C539
R506
R526
R
527
R528
R529
R531
R535
R503
R504
RR501
RR503
RR504
RR505
RR506
RR507
RR502
C521
C522
R513
R514
R515
R516
R517
R518
R519
R520
R521
R522
C503
C504
C507
C508
C510
C511
C513
C514
C515
C516
C517
C518
C529
C531
C530
C532
L502
R524
R
505
C501
C502
C527
C526
R
532
R533
R534
C520
C525
C524
C541
R512
C534
C533
C540
R
507
L501
10
µH
R530
L505
10
µH
R409
R408
R590
R509
PN503
L507
10
µH
R525
PN501
220
220
0.01
0.01
100
100
100
100
330
330
330
47k
1k
220
220
220
220
220
220
220
0.1
0.1
0
0
0
0
0
0
0
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
100
6.3V
100
6.3V
0.1
0.1
0
10k
330
1
100
6.3V
0.1
0.1
220
220
220
0.1
0.1
10
16V
0.1
4.7k
0.1
100
16V
8200p
5.1k
330
100
100
0
0
12P
0
30P
HD
D OUT
B2-4
B3-4
GND
5VU
3.3V
5VD
5VA
B4-6
B4-5
5VA
GND
5VM
3.3V
CDP 33M
8V
8VM
DIG IN
OPT IN
SDT DAC
SCK DAC
CS DAC
DA M
CLK
DA LRCK
DA DATA
DA CLK
AD M
CLK
AD BCK
AD DATA
DIG IN
OPT IN
AD BCK
DA CLK
DA DATA
DA LRCK
CS DAC
SCK DAC
SDT DAC
DA MCLK
DAC RST
AD LRCK
AD LRCK
RW DATA
RW LRCK
RW CLK
F DOUT
F DOUT
RW DOUT
/ATA CS3
ATA A2
ATA A1
ATA A0
/ATA CS1
/ATA RD
/ATA W
R
ROUT
DLRCK
DBCK
DA RCS
DA RCLK
DA RDATA
DUB START
SRC RST
SRC CS
SRC DIN
RXP
DAC RST
RXP
SW LRCK
SW BCK
SW DATA
SRC CLK
SRC DATA
SRC INT
SW
LRCK
SW
BCK
SW
DATA
AD DATA
AD M
CLK
RW
DOUT
/HD 4
/HD 10
/HD 5
/HD 9
/HD 6
/HD 8
/HD 7
/HD 15
/HD 0
/HD 14
/HD 1
/HD 13
/HD 2
/HD 12
/HD 3
/HD 11
RW DATA
RW LRCK
RW CLK
RW DOUT
CS1
CS1
PWR CTL
CDR
RST
FPGA AS
FPGA WD
FPGA CLK
FPGA CS
P LRCK
P DATA
P DOUT
-28V
-23V
-34V
AS PROG
P BCK
DAC CS
LEVEL IN
EXT RM
C
PW
R M
UTE
DUB SEL
LEVEL SEL
FPGA RST
CXD M
UTE
M
CLK IN
MCLK IN
EM
PH
RXP
RXN
VA+
AGND
FILT
RST
RM
CK
RERR
ILR
CK
ISCLK
SDIN
TXP
TXN
VD+
DGND
OM
CK
U
INT
SDOUT
OLRCK
OSCLK
TCBL
SDA/CDOUT
AD0/CS
SCL/CCLK
AD1/CDIN
H/S
GND
GND
GND
LEVEL SEL
DAC RST
DUB SEL
GND
SDT DAC
SCK DAC
CS DAC
F DOUT
DA M
CLK
GND
GND
GND
GND
DA LRCK
DA DATA
DA CLK
AD M
CLK
AD LRCK
AD BCK
AD DATA
FR DIG IN
OPT IN
DIG IN
SRC
R5S2 0
R5S3 0
IC502
R5Q1 100
1
5
10
15
20
25
30
ATA W
R
ATAPIL<15>
ATAPIL<0>
ATAPIL<14>
ATAPIL<13>
ATAPIL<12>
ATAPIL<2>
ATAPIL<1>
GND
VCC
ATAPIL<3>
ATAPIL<4>
ATAPIL<5>
ATAPIL<6>
ATAPIL<7>
ATAPIL<11>
ATAPIL<10>
ATAPIL<9>
ATAPIL<8>
GND
VCC
FPGACS 1
SCLK 1
SDATAO 1
DA PCS
DA PCLK
DA PDATA
P CLK
P IRCK
P DATA
GND
P DOUT
CS DAC
SCK DAC
DASDT C
RW DOUT
R OPT IN
DIG ON
MCLK IN
AD LRCK
DOUT
DA LRCKL
AD DATA
VCC
GND
SRC DATA
SRC CLK
SRC LRCK
DA DATA
M
CLK IN
DA CLK
RESET
AD M
CLK
NC
DAC M
CLK
GND
F75
TEST M
ODE
RW
DOUT
CS 1
OMCK
S D TXP
RW LRCK
RW CLK
RW DATA
SRC RXP
FPGA AS
S D DATA
S D LRCK
S D CLK
DUB SEL
DAC RST
DUB TRK INC
DUB START
DA XCK
DA RDATA
DA RCLK
DA RCS
INT
R5S1
0
CS8420-CSR
FPGA
VC0IS05
3.3V
PWR CTL
5VU
8V
5VA
AGND
5VD/M
GND
GND
-34V
-28V
-23V
CDR RST
R5T6 0
CXD MUTE
IC510
R4K1 100
R4K2 100
LEVEL IN
EXT RM
C
PW
R M
UTE
A DATA ZW
RO
R5T7 0

Sony RCD-W3 Specifications

Power

power requirements	U.S.A. and Canada 120 V AC, 60 Hz
power requirements other countries	110 – 240 V AC, 50/60 Hz
power consumption	20 W

Audio Specifications

frequency response	20 Hz – 20, 000 Hz (±0.5 dB)
signal-to-noise ratio	More than 100 dB
dynamic range	More than 95 dB

Inputs

analog in impedance	47 kilohms
rated input	330 mVrms
minimum input	125 mVrms

Outputs

analog out rated output	2 Vrms (at 50 kilohms)
load impedance	over 10 kilohms
phones	28 mW, 32 ohms

Weight and Dimensions

dimensions	430 × 108 × 368 mm
mass	4.6 kg